`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/07 08:38:44
// Design Name: 
// Module Name: crm_3class
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

`include "counter_def_class3.vh"
module crm_3class(
    input  wire clk,
    input  wire rst,
    output reg  clk_cnt,
    output wire rst_cnt
);
    reg [3:0] cnt;
    reg clk1;
    reg clk2;
    wire clk_out;
    always@(posedge clk or negedge rst)begin
        if(!rst)begin
            cnt<=2'd0;
        end
        else if(cnt==4)begin
            cnt<=0;
        end
        else begin
            cnt<=cnt+2'd1;
        end
    end

    always@(posedge clk or negedge rst)begin
        if(!rst)begin
            clk_cnt<=0;
        end
        else if(cnt==3) begin
            clk_cnt=~clk_cnt;
        end
    end
    
    always@(posedge clk or negedge rst)begin
        if(!rst)begin
            clk1<=0;
        end
        else if(cnt==2) begin
            clk1<=1;
        end
        else if(cnt==4) begin
            clk1<=0;
        end
        else begin
            clk1<=clk1;
        end
    end
  
    always@(negedge clk or negedge rst)begin
        if(!rst)begin
           clk2<=0;
        end
        else if(cnt==2) begin
            clk2<=1;
        end
        else if(cnt==4) begin
            clk2<=0;
        end
        else ;
    end
    
    always@(negedge clk or negedge rst)begin
        if(!rst)begin
           cnt<=0;
        end
        else if(cnt==4)begin
            cnt<=0;
        end
        else begin
            cnt<=cnt+1;
        end
    end
    
    assign clk_out = clk1 | clk2;
    //assign clk_cnt=clk;
    assign rst_cnt=rst;
   
    //---------------------------------
     reg flag;
    always@(negedge clk or negedge rst)begin
        if(!rst)begin
            flag<=0;
        end
        else if(cnt==2)begin
            flag<=1;
        end
        else if(cnt==4)begin
            flag<=0;
        end
    end
    
    
endmodule

